Volume 3, Issue 2, April 2015, Page: 19-24
An Optimized DAC Timing Strategy in SAR ADC with Considering the Overshoot Effect
M. Dashtbayazi, Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran
M. Sabaghi, Laser and Optics Research School, Nuclear Science and Technology Research Institute (NSTRI), Tehran, Iran
S. Marjani, Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran
Received: Mar. 2, 2015;       Accepted: Mar. 19, 2015;       Published: Apr. 2, 2015
DOI: 10.11648/j.jeee.20150302.12      View  5048      Downloads  333
Abstract
In this paper, we report an ultra-low power successive-approximation-register (SAR) analog-to digital converter (ADC) by using a DAC timing strategy with considering overshoot effect to increase the sampling rate. This ADC is simulated for power supplies voltage of 0.6 V and 1.2 V in a 130-nm CMOS technology. The results indicate an ENOB greater than 9.3 bits for its full sampling-rate range (4 to 32 MS/s) with an FOM=5.3 to 9.3 fJ/conv-step.
Keywords
Data Converter, Overshoot Effect, Asynchronous Process, Power Efficiency, DAC Timing Strategy, Low Power Designs
To cite this article
M. Dashtbayazi, M. Sabaghi, S. Marjani, An Optimized DAC Timing Strategy in SAR ADC with Considering the Overshoot Effect, Journal of Electrical and Electronic Engineering. Vol. 3, No. 2, 2015, pp. 19-24. doi: 10.11648/j.jeee.20150302.12
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