Research Article | | Peer-Reviewed

Influence of Parasitic Parameters on Switching Characteristics in Single and Paralleled Silicon Carbide Power MOSFETs

Received: 25 June 2025     Accepted: 9 July 2025     Published: 30 July 2025
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Abstract

This research evaluates the switching performance of silicon carbide (SiC) transistors compared to silicon (Si) transistors through a double pulse test. The performance was analyzed by measuring switching losses, di/dt, overshooting and switching times. The results demonstrated that switching losses, as well as rise and fall times, are reduced by half in SiC transistors. However, some overshoot in voltage and current waveforms was observed due to the high switching speed of SiC transistors. Subsequently, the impact of parasitic capacitive and inductive elements on the switching performance and switching losses in SiC transistors was studied across various values. The findings revealed that these parasitic components significantly affect the current balancing among SiC transistors in parallel driving circuits, with a recorded current difference of up to 6 A between transistors due to variations in internal capacitor values and the inductive effects resulting from current changes over time in the transistor's terminal paths. Simulation was conducted using LTspice software. In conclusion, the research results were summarized, and conclusions regarding the impact of internal elements on transistor performance were presented.

Published in Journal of Electrical and Electronic Engineering (Volume 13, Issue 4)
DOI 10.11648/j.jeee.20251304.14
Page(s) 184-204
Creative Commons

This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.

Copyright

Copyright © The Author(s), 2025. Published by Science Publishing Group

Keywords

Switching Losses, Static Current, Dynamic Current, Double Pulse Testing, Parasitic Inductance, Parasitic Capacitance, Current Balancing, Parallel SiC MOSFET

References
[1] Nektarios et al., (2023).” Active Autonomous Open-Loop Technique for Static and Dynamic Current Balancing of Parallel-Connected Silicon Carbide MOSFETs, energies journal.
[2] Jianing Guo. (2022). Analysis of Current Imbalance in Paralleled Silicon Carbide Power MOSFETs. Academic Journal of Science and Technology.
[3] Haihong Qin. et al. (2018). Influence of Parasitic Parameters on Switching Characteristics and Layout Design Considerations of SiC MOSFETs. Journal of Power Electronics.
[4] Y He. Et Al. (2024). Dynamic Current Balancing For Paralleled Sic Mosfets With Circuit Mismatches Considering Circulating Current In Drive Circuit. Cpss Transactions On Power Electronics And Applications.
[5] M. Eko Sulistyo. et al. (2023). A New Method Of The Active Gate Driver For Current Balancing In The Parallel MOSFET Circuits. Journal Of Novel Carbon Resource Sciences & Green Asia Strategy, Researchgate.
[6] Giannopoulos, N. et al. (2023). Active Autonomous Open-loop Technique For Static And Dynamic Current Balancing Of Parallel-connected Silicon Carbide Mosfets. Energies Journal.
[7] Shuang Zhao. et al. (2023). Digital Close-loop Active Gate Driver For Static And Dynamic Current Sharing Of Paralleled Sic Mosfets. Ieee Journal of Emerging and Selected Topics in Power Electronics.
[8] Shuang Zhao. et al. (2023). Parallel Connection of Silicon Carbide MOSFETs - Challenges, Mechanism, and Solutions. IEEE Transactions on Power Electronics.
[9] Zhang S (2023), Influence of driving and parasitic parameters on the switching behaviors of the SiC MOSFET. Front. Energy Res. 10: 1079623.
[10] Y. He, X. Wang, S. Shao and J. Zhang, “Active gate driver for dynamic current balancing of parallel-connected SiC MOSFETs,” IEEE Trans. Power Electron., vol. 38, no. 2, pp. 6116-6127, May 2023.
[11] L. Du, Y. Wei, X. Du, A. Stratta, Z. Saadatizadeh and H. A. Mantooth, “Digital active gate driving system for paralleled SiC MOSFETs with closed-loop current balancing control,” in IEEE Trans. Energy Convers., Detroit, MI, USA, 2022.
[12] L. Du, H. Cao, Z. Saadatizadeh, Y. Zhao and H. A. Mantooth, “A simple switching-event dependent high-frequency sampling method for power conversion system,” IEEE Trans. Power Electron., vol. 38, no. 6, pp. 6880 - 6885, 2023.
[13] Bendik Nybakk Torsæter,(2016).” Evaluation of Switching Characteristics, Switching Losses and Snubber Design for a Full SiC Half-Bridge Power Module”, Norwegian University of Science and Technology.
[14] MING SU, et al., (2020),” SOLVING THE CHALLENGES OF DRIVING SIC MOSFETS”, DESIGNLINES.
[15] JONATHAN TUCKER, (2023).” Automate double-pulse testing in WBG devices”, TEKTRONIX.
Cite This Article
  • APA Style

    Kassem, O. A., Zaidan, N. (2025). Influence of Parasitic Parameters on Switching Characteristics in Single and Paralleled Silicon Carbide Power MOSFETs. Journal of Electrical and Electronic Engineering, 13(4), 184-204. https://doi.org/10.11648/j.jeee.20251304.14

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    ACS Style

    Kassem, O. A.; Zaidan, N. Influence of Parasitic Parameters on Switching Characteristics in Single and Paralleled Silicon Carbide Power MOSFETs. J. Electr. Electron. Eng. 2025, 13(4), 184-204. doi: 10.11648/j.jeee.20251304.14

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    AMA Style

    Kassem OA, Zaidan N. Influence of Parasitic Parameters on Switching Characteristics in Single and Paralleled Silicon Carbide Power MOSFETs. J Electr Electron Eng. 2025;13(4):184-204. doi: 10.11648/j.jeee.20251304.14

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  • @article{10.11648/j.jeee.20251304.14,
      author = {Osama al Kassem and Nidal Zaidan},
      title = {Influence of Parasitic Parameters on Switching Characteristics in Single and Paralleled Silicon Carbide Power MOSFETs
    },
      journal = {Journal of Electrical and Electronic Engineering},
      volume = {13},
      number = {4},
      pages = {184-204},
      doi = {10.11648/j.jeee.20251304.14},
      url = {https://doi.org/10.11648/j.jeee.20251304.14},
      eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.jeee.20251304.14},
      abstract = {This research evaluates the switching performance of silicon carbide (SiC) transistors compared to silicon (Si) transistors through a double pulse test. The performance was analyzed by measuring switching losses, di/dt, overshooting and switching times. The results demonstrated that switching losses, as well as rise and fall times, are reduced by half in SiC transistors. However, some overshoot in voltage and current waveforms was observed due to the high switching speed of SiC transistors. Subsequently, the impact of parasitic capacitive and inductive elements on the switching performance and switching losses in SiC transistors was studied across various values. The findings revealed that these parasitic components significantly affect the current balancing among SiC transistors in parallel driving circuits, with a recorded current difference of up to 6 A between transistors due to variations in internal capacitor values and the inductive effects resulting from current changes over time in the transistor's terminal paths. Simulation was conducted using LTspice software. In conclusion, the research results were summarized, and conclusions regarding the impact of internal elements on transistor performance were presented.},
     year = {2025}
    }
    

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    T1  - Influence of Parasitic Parameters on Switching Characteristics in Single and Paralleled Silicon Carbide Power MOSFETs
    
    AU  - Osama al Kassem
    AU  - Nidal Zaidan
    Y1  - 2025/07/30
    PY  - 2025
    N1  - https://doi.org/10.11648/j.jeee.20251304.14
    DO  - 10.11648/j.jeee.20251304.14
    T2  - Journal of Electrical and Electronic Engineering
    JF  - Journal of Electrical and Electronic Engineering
    JO  - Journal of Electrical and Electronic Engineering
    SP  - 184
    EP  - 204
    PB  - Science Publishing Group
    SN  - 2329-1605
    UR  - https://doi.org/10.11648/j.jeee.20251304.14
    AB  - This research evaluates the switching performance of silicon carbide (SiC) transistors compared to silicon (Si) transistors through a double pulse test. The performance was analyzed by measuring switching losses, di/dt, overshooting and switching times. The results demonstrated that switching losses, as well as rise and fall times, are reduced by half in SiC transistors. However, some overshoot in voltage and current waveforms was observed due to the high switching speed of SiC transistors. Subsequently, the impact of parasitic capacitive and inductive elements on the switching performance and switching losses in SiC transistors was studied across various values. The findings revealed that these parasitic components significantly affect the current balancing among SiC transistors in parallel driving circuits, with a recorded current difference of up to 6 A between transistors due to variations in internal capacitor values and the inductive effects resulting from current changes over time in the transistor's terminal paths. Simulation was conducted using LTspice software. In conclusion, the research results were summarized, and conclusions regarding the impact of internal elements on transistor performance were presented.
    VL  - 13
    IS  - 4
    ER  - 

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Author Information
  • Department of Electronics and Communication Engineering, Faculty of Mechanical and Electrical Engineering, Damascus University, Damascus, Syria

  • Department of Electronics and Communication Engineering, Faculty of Mechanical and Electrical Engineering, Damascus University, Damascus, Syria

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